With the increase in integration density of semiconductor memory devices, many approaches have been used to increase the capacitance of a capacitor in a limited cell area. Some of the approaches used include a method of increasing the electric field created in the capacitor by reducing the thickness of a dielectric film of the capacitor, and a method of increasing the effective area of a capacitor by designing the lower electrode of the capacitor to have a three-dimensional structure.
However, even if these methods are applied in the manufacture of semiconductor memory devices, if a common capacitor dielectric film, such as TiO.sub.2 or SiO.sub.2 is employed, a sufficient capacitance typically cannot be secured for the operation of a semiconductor memory device having an integration density of 1 gigabits or more. To address this problem, great interest has been focused on a method of forming the capacitor dielectric film with a ferroelectric or high-dielectric film, such as (Ba,Sr)Ti0.sub.3 (BST), PbZrTiO.sub.3 (PZT) and (Pb,La)(Zr,Ti)O.sub.3 (PLZT).
For example, according to a conventional method for manufacturing a semiconductor memory device having a capacitor dielectric film formed of a high-dielectric film or ferroelectric film, first, a lower electrode pad is formed of a doped polysilicon on an impurity injection region of a semiconductor substrate. After formation of a lower electrode contact electrically connected to the lower electrode pad, a capacitor lower electrode is formed on the lower electrode contact. Next, a capacitor dielectric film is formed of a high-dielectric film or ferroelectric film on the capacitor lower electrode. To crystalize the capacitor dielectric film to give enhanced insulation characteristics, i.e., higher capacitance and lower leakage current of the capacitor, the capacitor dielectric film is subjected to a high-temperature heat treatment in an oxygen atmosphere. However, if the high-temperature heat treatment is carried out at high temperatures as high as 600 to 900.degree. C. under an oxygen atmosphere, and if the capacitor lower electrode is formed of a common doped polysilicon, contact resistance can be degraded due to oxidation of the capacitor lower electrode during the high-temperature heat treatment. In addition, there is a problem in that a metal silicide layer is formed between the capacitor dielectric film and the capacitor lower electrode.
For this reason, when a capacitor of a semiconductor memory device is formed using a high-dielectric or ferroelectric layer, the platinum (Pt) group elements in the Periodic Table, or an oxide of these elements, for example, Pt, iridium (Ir), ruthenium (Ru), RuO.sub.2, or IrO.sub.2 is commonly used as an electrode material.
In the conventional method, for the formation of the lower electrode with a Pt group metal, a conductive film is formed of a Pt group metal and patterned into a lower electrode by a dry etching method. However, it is not easy to convert the Pt group metal forming the conductive layer into volatile gases by dry etching, and thus there is a problem in separating the lower electrode into individual unit cells. Thus, the dry etching method has a limitation in forming a semiconductor memory device whose lower electrode has a width of 300 nm or less, especially in forming a semiconductor memory device having an integration density of 4 gigabits or more. Due to this drawback of the dry etching technique, a variety of methods for the formation of a capacitor lower electrode have been suggested.
Another conventional method of forming a capacitor lower electrode with a Pt group metal by electroplating will be described. FIGS. 1A through 1C are sectional views of successive stages of a conventional method for forming a capacitor lower electrode with a Pt layer by electroplating.
Referring to FIG. 1A, a lower electrode pad 12 formed of a conductive polysilicon is formed in the impurity injection region (not shown) of a semiconductor substrate 10. This impurity injection region may constitute a source/drain region of a memory cell access transistor. Next, an interlevel dielectric (ILD) film 14, which electrically isolates spatially adjacent lower electrode pads 12, is formed over the lower electrode pad 12. The ILD film 14 is patterned by photolithography to form an opening 16 exposing the lower electrode pad 12, and a lower electrode seed layer 18 formed of a Pt group metal is deposited over the bottom surface and sidewalls of the opening 16, and the top of the ILD film 14. Following this, a plating mask pattern 20 is formed around the opening 16. The plating mask pattern 20 defines the shape of the lower electrode by exposing a region of the lower electrode seed layer on which a lower electrode is formed.
After the formation of the lower electrode seed layer 18 and the plating mask pattern 20, a process of forming a capacitor lower electrode is carried out by electroplating. For example, for a capacitor lower electrode formed of Pt, the semiconductor substrate 10 is immersed into a plating solution containing Pt salt. Next, the cathode of a power source 22 is connected to the lower electrode seed layer 18 by a first wire 24, while the anode of the power source 22 is connected to a Pt source electrode 28 by a second wire 26. As a result, a Pt layer is deposited on the lower electrode seed layer 18 to the same level as the top of the plating mask pattern 20. A portion of the Pt layer filling the opening 16 (i.e., in the lower region from dashed lines in FIG. 1A) forms a lower electrode contact 30, and the other portion of Pt layer on the lower electrode contact 30 forms a capacitor lower electrode 32.
Referring to FIG. 1B, after the formation of the lower electrode contact 30 and the capacitor lower electrode 32 by electroplating, the plating mask pattern 20 is removed by wet etching. Then, the lower electrode seed layer 18 on top of the ILD film 14, which is exposed by the removal of the plating mask pattern 20, is removed to separate the lower electrode 32 in cell units.
Here, in the case where the lower electrode seed layer 18 is formed of Pt, a dry etching technique typically should be applied in removing the lower electrode seed layer 18 exposed by the removal of the plating mask pattern 20. However, it is not easy to convert Pt of the lower electrode seed layer 18 into volatile gases by dry etching to separate individual capacitor lower electrode cells. Particularly for the fabrication of a semiconductor memory device having a design rule of 0.15 .mu.m or less, a pitch of the lower electrode seed layer 18 between adjacent lower electrodes 32 is further decreased, so that separating the capacitor lower electrode in cell units becomes more difficult.
To solve this problem, a method of forming the lower electrode seed layer 18 with ruthenium (Ru), which can be easily converted into volatile compounds by dry etching, has been suggested. However, when the lower electrode seed layer 18 is formed of Ru, a Pt--Ru alloy is formed in the interface between the lower electrode contact 30 formed of Pt and the lower electrode seed layer 18 remaining after node separation, which causes a problem in a subsequent heat treatment of a capacitor dielectric film. This will be described with reference to FIG. 1C.
Referring to FIG. 1C, after separation of the capacitor lower electrode 32 into unit cells by a node separation process, a ferroelectric material or a high-dielectric material is deposited over the resulting structure to form a dielectric film 33. Next, a high-temperature heat treatment (indicated by arrows) is carried out in an oxygen atmosphere so as to enhance the insulating characteristics of the dielectric film 33. However, in the case where the lower electrode seed layer 18 is formed of Ru, a Pt--Ru alloy is formed in the interface between the lower electrode seed layer 18 formed of Ru, which is left after node separation, and the lower electrode contact 30 formed of Pt. Ru of the alloy, which has a weak oxidation resistance, compared to Pt, is oxidized when the dielectric layer 33 is subjected to a high-temperature heat treatment process. The formation of a Ru oxide, which has a larger volume than Pt, in the high-temperature treatment process on the dielectric layer 33 changes the morphology of the capacitor lower electrode 32, which applies a physical stress to the dielectric layer 33. As a result, the interfacial properties between the capacitor lower electrode 32 and the dielectric film 33 are degraded, thereby increasing the leakage current of the capacitor.